(define_attr "type" "t_branch,t_call,t_mem,t_mem_double,t_other" (const_string "t_other"))

(define_attr "length" "" (const_int 1))

;; These two `define_delay's can not be defined at the same time.

(define_delay (eq_attr "type" "t_branch")
  [(and (eq_attr "type" "t_other")
	(eq_attr "length" "1"))
   (nil)
   (nil)
   (and (eq_attr "type" "t_other")
	(eq_attr "length" "1"))
   (nil)
   (nil)
   (and (eq_attr "type" "t_other")
	(eq_attr "length" "1"))
   (nil)
   (nil)])

(define_delay (eq_attr "type" "t_call")
  [(and (eq_attr "type" "t_other")
	(eq_attr "length" "1"))
   (nil)
   (nil)])

(define_delay (eq_attr "type" "t_mem")
  [(and (eq_attr "type" "t_other")
	(eq_attr "length" "1"))
   (nil)
   (nil)])

(define_delay (eq_attr "type" "t_mem_double")
  [(and (eq_attr "type" "t_other")
	(eq_attr "length" "1"))
   (nil)
   (nil)
   (and (eq_attr "type" "t_other")
	(eq_attr "length" "1"))
   (nil)
   (nil)])

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

(define_insn "tsu_nop"
  [(const_int 0)]
  ""
  "nop")

(define_insn "tsu_and"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(and:QI (match_operand:QI 1 "register_operand" "%r")
		(match_operand:QI 2 "register_operand" "r")))]
  ""
  "and\\t%1, %2, %0")

(define_insn "tsu_or"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(ior:QI (match_operand:QI 1 "register_operand" "%r")
		(match_operand:QI 2 "register_operand" "r")))]
  ""
  "or\\t%1, %2, %0")

(define_insn "tsu_xor"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(xor:QI (match_operand:QI 1 "register_operand" "%r")
		(match_operand:QI 2 "register_operand" "r")))]
  ""
  "xor\\t%1, %2, %0")

(define_insn "tsu_not"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(not:QI (match_operand:QI 1 "register_operand" "r")))]
  ""
  "not\\t%1, %0")

(define_insn "tsu_add"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(plus:QI (match_operand:QI 1 "register_operand" "%r")
		 (match_operand:QI 2 "register_operand" "r")))]
  ""
  "add\\t%1, %2, %0")

(define_insn "tsu_sub"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(minus:QI (match_operand:QI 1 "register_operand" "r")
		  (match_operand:QI 2 "register_operand" "r")))]
  ""
  "sub\\t%1, %2, %0")

(define_insn "tsu_add1"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(plus:QI (match_operand:QI 1 "register_operand" "r")
		 (const_int 1)))]
  ""
  "add1\\t%1, %0")

(define_insn "tsu_sub1"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(minus:QI (match_operand:QI 1 "register_operand" "r")
		  (const_int 1)))]
  ""
  "sub1\\t%1, %0")

(define_insn "tsu_shr1"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(lshiftrt:QI (match_operand:QI 1 "register_operand" "r")
		     (const_int 1)))]
  ""
  "shr1\\t%1, %0")

(define_insn "tsu_shl1"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(ashift:QI (match_operand:QI 1 "register_operand" "r")
		   (const_int 1)))]
  ""
  "shl1\\t%1, %0")

(define_insn "tsu_shr2"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(lshiftrt:QI (match_operand:QI 1 "register_operand" "r")
		     (const_int 2)))]
  ""
  "shr2\\t%1, %0")

(define_insn "tsu_shl2"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(ashift:QI (match_operand:QI 1 "register_operand" "r")
		   (const_int 2)))]
  ""
  "shl2\\t%1, %0")

(define_insn "tsu_lshr1"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(ior:QI (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
			     (const_int 1))
		(ashift:QI (match_operand:QI 2 "register_operand" "r")
			   (const_int 15))))]
  ""
  "lshr1\\t%0, %2")

(define_insn "tsu_lshl1"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(ior:QI (ashift:QI (match_operand:QI 1 "register_operand" "0")
			   (const_int 1))
		(lshiftrt:QI (match_operand:QI 2 "register_operand" "r")
			     (const_int 15))))]
  ""
  "lshl1\\t%0, %2")

(define_insn "tsu_lshr2"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(ior:QI (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
			     (const_int 2))
		(ashift:QI (match_operand:QI 2 "register_operand" "r")
			   (const_int 14))))]
  ""
  "lshr2\\t%0, %2")

(define_insn "tsu_lshl2"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(ior:QI (ashift:QI (match_operand:QI 1 "register_operand" "0")
			   (const_int 2))
		(lshiftrt:QI (match_operand:QI 2 "register_operand" "r")
			     (const_int 14))))]
  ""
  "lshl2\\t%0, %2")

(define_insn "tsu_gethh"
  [(set (match_operand:QI 0 "register_operand" "=r,r")
	(ior:QI (and:QI (match_operand:QI 1 "register_operand" "0,r")
			(const_int 65280))
		(lshiftrt:QI (match_operand:QI 2 "register_operand" "r,0")
			     (const_int 8))))]
  ""
  "@
   gethh1\\t%0, %2
   gethh2\\t%0, %1")

(define_insn "tsu_gethl"
  [(set (match_operand:QI 0 "register_operand" "=r,r")
	(ior:QI (and:QI (match_operand:QI 1 "register_operand" "0,r")
			(const_int 65280))
		(and:QI (match_operand:QI 2 "register_operand" "r,0")
			(const_int 255))))]
  ""
  "@
   gethl1\\t%0, %2
   gethl2\\t%0, %1")

(define_insn "tsu_getlh"
  [(set (match_operand:QI 0 "register_operand" "=r,r")
	(ior:QI (and:QI (match_operand:QI 1 "register_operand" "0,r")
			(const_int 255))
		(and:QI (match_operand:QI 2 "register_operand" "r,0")
			(const_int 65280))))]
  ""
  "@
   getlh1\\t%0, %2
   getlh2\\t%0, %1")

(define_insn "tsu_getll"
  [(set (match_operand:QI 0 "register_operand" "=r,r")
	(ior:QI (ashift:QI (match_operand:QI 1 "register_operand" "0,r")
			   (const_int 8))
		(and:QI (match_operand:QI 2 "register_operand" "r,0")
			(const_int 255))))]
  ""
  "@
   getll1\\t%0, %2
   getll2\\t%0, %1")

(define_insn "tsu_mulhh_load"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(mult:QI (lshiftrt:QI (match_operand:QI 1 "register_operand" "%r")
			      (const_int 8))
		 (lshiftrt:QI (match_operand:QI 2 "register_operand" "r")
			      (const_int 8))))]
  ""
  "*
{
  return tsu_fill_delay_slot (1,
			      \"mulhh\\t%1, %2\;\"
			      \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\;\"
			      \"load\\t%0\");
}"
  [(set_attr "type" "t_mem")
   (set_attr "length" "3")])

(define_insn "tsu_mulhl_load"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(mult:QI (lshiftrt:QI (match_operand:QI 1 "register_operand" "r")
			      (const_int 8))
		 (and:QI (match_operand:QI 2 "register_operand" "r")
			 (const_int 255))))]
  ""
  "*
{
  return tsu_fill_delay_slot (1,
			      \"mulhl\\t%1, %2\;\"
			      \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\;\"
			      \"load\\t%0\");
}"
  [(set_attr "type" "t_mem")
   (set_attr "length" "3")])

(define_insn "tsu_mullh_load"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(mult:QI (and:QI (match_operand:QI 1 "register_operand" "r")
			 (const_int 255))
		 (lshiftrt:QI (match_operand:QI 2 "register_operand" "r")
			      (const_int 8))))]
  ""
  "*
{
  return tsu_fill_delay_slot (1,
			      \"mullh\\t%1, %2\;\"
			      \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\;\"
			      \"load\\t%0\");
}"
  [(set_attr "type" "t_mem")
   (set_attr "length" "3")])

(define_insn "tsu_mulll_load"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(mult:QI (and:QI (match_operand:QI 1 "register_operand" "%r")
			 (const_int 255))
		 (and:QI (match_operand:QI 2 "register_operand" "r")
			 (const_int 255))))]
  ""
  "*
{
  return tsu_fill_delay_slot (1,
			      \"mulll\\t%1, %2\;\"
			      \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\;\"
			      \"load\\t%0\");
}"
  [(set_attr "type" "t_mem")
   (set_attr "length" "3")])

(define_insn "tsu_addr_load"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(match_operand:QI 1 "memory_operand" "m"))]
  ""
  "*
{
  return tsu_fill_delay_slot (1,
			      \"addr\\t%1\;\"
			      \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\;\"
			      \"load\\t%0\");
}"
  [(set_attr "type" "t_mem")
   (set_attr "length" "3")])

(define_insn "tsu_store"
  [(set (match_operand:QI 0 "memory_operand" "=m")
	(match_operand:QI 1 "register_operand" "r"))]
  ""
  "*
{
  static char buf [1000];
  rtx exp, exp0, exp1;
  int regno, intval;

  exp = XEXP (operands [0], 0);

  if (GET_CODE (exp) == PLUS) {
    exp0 = XEXP (exp, 0);
    exp1 = XEXP (exp, 1);

    if (GET_CODE (exp0) == CONST_INT) {
      intval = INTVAL (exp0);
      regno = REGNO (exp1);
    } else /* if (GET_CODE (exp1) == CONST_INT) */ {
      regno = REGNO (exp0);
      intval = INTVAL (exp1);
    }

    if (intval >= 32) {
      sprintf (buf,
	       \"set\\t%d, r15\;\"
	       \"add\\tr15, r%d, r15\;\"
	       \"store\\tr15 + 0, %%1\;\"
	       \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\",
	       intval,
	       regno);

      return tsu_fill_delay_slot (1, buf);
    }
  }

  return tsu_fill_delay_slot (1,
			      \"store\\t%0, %1\;\"
			      \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\");
}"
  [(set_attr "type" "t_mem")
   (set_attr "length" "5")])

(define_insn "tsu_mov"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(match_operand:QI 1 "register_operand" "r"))]
  ""
  "mov\\t%1, %0")

(define_insn "tsu_zero"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(const_int 0))]
  ""
  "zero\\t%0")

(define_insn "tsu_set"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(match_operand:QI 1 "immediate_operand" "i"))]
  ""
  "set\\t%1, %0"
  [(set_attr "length" "2")])

(define_insn "tsu_rj"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
  "* return tsu_fill_delay_slot (3, \"j\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjeq"
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j==\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjne"
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j!=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjgt"
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjlt"
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjge"
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjle"
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjgtu"
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjltu"
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjgeu"
  [(set (pc)
	(if_then_else (geu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjleu"
  [(set (pc)
	(if_then_else (leu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjeq_inv"
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return tsu_fill_delay_slot (3, \"j!=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjne_inv"
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return tsu_fill_delay_slot (3, \"j==\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjgtu_inv"
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjltu_inv"
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjgeu_inv"
  [(set (pc)
	(if_then_else (geu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjleu_inv"
  [(set (pc)
	(if_then_else (leu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjgt_inv"
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjlt_inv"
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjge_inv"
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_rjle_inv"
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_aj"
  [(set (pc)
	(match_operand:QI 0 "register_operand" "r"))]
  ""
  "* return tsu_fill_delay_slot (3, \"j\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajeq"
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (match_operand:QI 0 "register_operand" "r")
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j==\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajne"
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (match_operand:QI 0 "register_operand" "r")
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j!=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajgtu"
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (match_operand:QI 0 "register_operand" "r")
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajltu"
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (match_operand:QI 0 "register_operand" "r")
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajgeu"
  [(set (pc)
	(if_then_else (geu (cc0)
			   (const_int 0))
		      (match_operand:QI 0 "register_operand" "r")
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajleu"
  [(set (pc)
	(if_then_else (leu (cc0)
			   (const_int 0))
		      (match_operand:QI 0 "register_operand" "r")
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajgt"
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (match_operand:QI 0 "register_operand" "r")
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajlt"
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (match_operand:QI 0 "register_operand" "r")
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajge"
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (match_operand:QI 0 "register_operand" "r")
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajle"
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (match_operand:QI 0 "register_operand" "r")
		      (pc)))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajeq_inv"
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (pc)
		      (match_operand:QI 0 "register_operand" "r")))]
  ""
  "* return tsu_fill_delay_slot (3, \"j!=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajne_inv"
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (pc)
		      (match_operand:QI 0 "register_operand" "r")))]
  ""
  "* return tsu_fill_delay_slot (3, \"j==\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajgtu_inv"
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (pc)
		      (match_operand:QI 0 "register_operand" "r")))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajltu_inv"
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (pc)
		      (match_operand:QI 0 "register_operand" "r")))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajgeu_inv"
  [(set (pc)
	(if_then_else (geu (cc0)
			   (const_int 0))
		      (pc)
		      (match_operand:QI 0 "register_operand" "r")))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajleu_inv"
  [(set (pc)
	(if_then_else (leu (cc0)
			   (const_int 0))
		      (pc)
		      (match_operand:QI 0 "register_operand" "r")))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajgt_inv"
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (pc)
		      (match_operand:QI 0 "register_operand" "r")))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajlt_inv"
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (pc)
		      (match_operand:QI 0 "register_operand" "r")))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>=\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajge_inv"
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (pc)
		      (match_operand:QI 0 "register_operand" "r")))]
  ""
  "* return tsu_fill_delay_slot (3, \"j<\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_ajle_inv"
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (pc)
		      (match_operand:QI 0 "register_operand" "r")))]
  ""
  "* return tsu_fill_delay_slot (3, \"j>\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_tablejump"
  [(set (pc)
	(match_operand:QI 0 "register_operand" "r"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "* return tsu_fill_delay_slot (3, \"j\\t%0\"); "
  [(set_attr "type" "t_branch")
   (set_attr "length" "4")])

(define_insn "tsu_call_imm"
  [(call (mem:QI (match_operand 0 "immediate_operand" "i"))
	 (match_operand 1 "" ""))
   (clobber (reg:QI 13))]
  ""
  "*
{
  return tsu_fill_delay_slot (1,
			      \"set\\t%0, r13\;\"
			      \"j\\tr13\;\"
			      \"set\\t1f.+1, r13\\n\"
			      \"1:\");
}"
  [(set_attr "type" "t_call")
   (set_attr "length" "6")])

(define_insn "tsu_call_value_imm"
  [(set (reg:HI 0)
	(call (mem:QI (match_operand 0 "immediate_operand" "i"))
	      (match_operand 1 "" "")))
   (clobber (reg:QI 13))]
  ""
  "*
{
  return tsu_fill_delay_slot (1,
			      \"set\\t%0, r13\;\"
			      \"j\\tr13\;\"
			      \"set\\t1f.+1, r13\\n\"
			      \"1:\");
}"
  [(set_attr "type" "t_call")
   (set_attr "length" "6")])

(define_insn "tsu_call"
  [(call (mem:QI (match_operand:QI 0 "register_operand" "r"))
	 (match_operand 1 "" ""))
   (clobber (reg:QI 13))]
  ""
  "*
{
  return tsu_fill_delay_slot (1,
			      \"j\\t%0\;\"
			      \"set\\t1f.+1, r13\\n\"
			      \"1:\");
}"
  [(set_attr "type" "t_call")
   (set_attr "length" "4")])

(define_insn "tsu_call_value"
  [(set (reg:HI 0)
	(call (mem:QI (match_operand:QI 0 "register_operand" "r"))
	      (match_operand 1 "" "")))
   (clobber (reg:QI 13))]
  ""
  "*
{
  return tsu_fill_delay_slot (1,
			      \"j\\t%0\;\"
			      \"set\\t1f.+1, r13\\n\"
			      \"1:\");
}"
  [(set_attr "type" "t_call")
   (set_attr "length" "4")])

(define_insn "tsu_testu"
  [(set (cc0)
	(match_operand:QI 0 "register_operand" "r"))
   (clobber (match_scratch:QI 1 "=&r"))]
  "! tsu_next_cc0_user_is_signed (insn)"
  "*
{
  return (\"\\t\\t; begin testu\;\"
	  \"test\\t%0\;\"
	  \"\\t\\t; end testu\;\"
	  \"\\t\\t; %1 is free\");
}")

(define_insn "tsu_tests"
  [(set (cc0)
	(match_operand:QI 0 "register_operand" "r"))
   (clobber (match_scratch:QI 1 "=&r"))]
  "tsu_next_cc0_user_is_signed (insn)"
  "\\t\\t; begin tests\;add\\t%0, %0, r15\;jc\\t1f\;nop\;zero\\tr15\;cmp\\tr15, %0\;zero\\tr15\;cmp\\t%0, r15\\n1:\;\\t\\t; end tests\;\\t\\t; %1 is free"
  [(set_attr "length" "7")])

(define_insn "tsu_cmpu"
  [(set (cc0)
	(compare (match_operand:QI 0 "register_operand" "r")
		 (match_operand:QI 1 "register_operand" "r")))
   (clobber (match_scratch:QI 2 "=&r"))]
  "! tsu_next_cc0_user_is_signed (insn)"
  "*
{
  return (\"\\t\\t; begin cmpu\;\"
	  \"cmp\\t%0, %1\;\"
	  \"\\t\\t; end cmpu\;\"
	  \"\\t\\t; %2 is free\");
}")

(define_insn "tsu_cmps"
  [(set (cc0)
	(compare (match_operand:QI 0 "register_operand" "r")
		 (match_operand:QI 1 "register_operand" "r")))
   (clobber (match_scratch:QI 2 "=&r"))]
  "tsu_next_cc0_user_is_signed (insn)"
  "*
{
  return (\"\\t\\t; begin cmps\;\"
	  \"xor\\t%0, %1, r15\;\"
	  \"add\\tr15, r15, r15\;\"
	  \"jc\\t1f\;\"
	  \"nop\;\"
	  \"nop\;\"
	  \"cmp\\t%1, %0\;\"
	  \"cmp\\t%0, %1\\n\"
	  \"1:\;\"
	  \"\\t\\t; end cmps\;\"
	  \"\\t\\t; %2 is free\");
}"
  [(set_attr "length" "7")])

(define_insn "tsu_neg"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(neg:QI (match_operand:QI 1 "register_operand" "r")))]
  ""
  "not\\t%1, %0\;add1\\t%0, %0"
  [(set_attr "length" "2")])

(define_split
  [(set (match_operand:QI 0 "register_operand" "=r")
	(neg:QI (match_operand:QI 1 "register_operand" "r")))]
  ""
  [(set (match_operand:QI 0 "register_operand" "=r")
	(neg:QI (match_operand:QI 1 "register_operand" "r")))]
  "
{
  emit_insn (gen_tsu_not (operands [0],
			  operands [1]));
  emit_insn (gen_tsu_add1 (operands [0],
			   operands [0]));

  DONE;
}")

(define_insn "tsu_abs"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(abs:QI (match_operand:QI 1 "register_operand" "r")))]
  ""
  "*
{
  return (\"\\t\\t; begin abs\;\"
	  \"add\\t%1, %1, r15\;\"
	  \"jnc\\t1f\;\"
	  \"not\\t%1, r15\;\"
	  \"add1\\tr15, r15\;\"
	  \"mov\\t%1, %0\;\"
	  \"mov\\tr15, %0\\n\"
	  \"1:\;\"
	  \"\\t\\t; end abs\");
}"
  [(set_attr "length" "6")])

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

(define_insn "tsu_dbl_double"
  [(set (match_operand:HF 0 "register_operand" "=r")
	(plus:HF (match_operand:HF 1 "register_operand" "r")
		 (match_dup 1)))]
  ""
  "*
{
  return (\"\\t\\t; begin fdbl\;\"
	  \"mov\\t%1_1, %0_1\;\"
	  \"jnt\\t1f\;\"
	  \"mov\\t%1_0, %0_0\;\"
	  \"mov\\t%1_1.H, r15.L\;\"
	  \"inc\\tr15\;\"
	  \"mov\\tr15.L, %0_1.H\\n\"
	  \"1:\;\"
	  \"\\t\\t; end fdbl\");
}"
  [(set_attr "length" "6")])

(define_insn "tsu_add_double"
  [(set (match_operand:HF 0 "register_operand" "=&r")
	(plus:HF (match_operand:HF 1 "register_operand" "%r")
		 (match_operand:HF 2 "register_operand" "r")))
   (clobber (reg:QI 13))
   (clobber (match_dup 1))
   (clobber (match_dup 2))
   (clobber (match_scratch:QI 3 "=&r"))
   (clobber (match_scratch:QI 4 "=&r"))]
  ""
  "*
{
  if (REGNO (operands [1]) < REGNO (operands [2])) {
    if (REGNO (operands [3]) < REGNO (operands [4])) {
      return tsu_fill_delay_slot (1, \"fcall\\tfadd@%1@%2@%0@%3@%4\");
    } else {
      return tsu_fill_delay_slot (1, \"fcall\\tfadd@%1@%2@%0@%4@%3\");
    }
  } else {
    if (REGNO (operands [3]) < REGNO (operands [4])) {
      return tsu_fill_delay_slot (1, \"fcall\\tfadd@%2@%1@%0@%3@%4\");
    } else {
      return tsu_fill_delay_slot (1, \"fcall\\tfadd@%2@%1@%0@%4@%3\");
    }
  }
}"
  [(set_attr "length" "6")
   (set_attr "type" "t_call")])

(define_insn "tsu_sub_double"
  [(set (match_operand:HF 0 "register_operand" "=&r")
	(minus:HF (match_operand:HF 1 "register_operand" "r")
		  (match_operand:HF 2 "register_operand" "r")))
   (clobber (reg:QI 13))
   (clobber (match_dup 1))
   (clobber (match_dup 2))
   (clobber (match_scratch:QI 3 "=&r"))
   (clobber (match_scratch:QI 4 "=&r"))]
  ""
  "*
{
  if (REGNO (operands [3]) < REGNO (operands [4])) {
    return tsu_fill_delay_slot (1, \"fcall\\tfsub@%1@%2@%0@%3@%4\");
  } else {
    return tsu_fill_delay_slot (1, \"fcall\\tfsub@%1@%2@%0@%4@%3\");
  }
}"
  [(set_attr "length" "6")
   (set_attr "type" "t_call")])

(define_insn "tsu_sq_double"
  [(set (match_operand:HF 0 "register_operand" "=&r")
	(mult:HF (match_operand:HF 1 "register_operand" "r")
		 (match_dup 1)))
   (clobber (match_dup 1))
   (clobber (reg:QI 13))]
  ""
  "* return tsu_fill_delay_slot (1, \"fcall\\tfsq@%1@%0\"); "
  [(set_attr "length" "6")
   (set_attr "type" "t_call")])

(define_insn "tsu_mul_double"
  [(set (match_operand:HF 0 "register_operand" "=&r")
	(mult:HF (match_operand:HF 1 "register_operand" "%r")
		 (match_operand:HF 2 "register_operand" "r")))
   (clobber (match_dup 1))
   (clobber (match_dup 2))
   (clobber (reg:QI 13))]
  ""
  "*
{
  if (REGNO (operands [1]) < REGNO (operands [2])) {
    return tsu_fill_delay_slot (1, \"fcall\\tfmul@%1@%2@%0\");
  } else {
    return tsu_fill_delay_slot (1, \"fcall\\tfmul@%2@%1@%0\");
  }
}"
  [(set_attr "length" "6")
   (set_attr "type" "t_call")])

(define_insn "tsu_div_double"
  [(set (match_operand:HF 0 "register_operand" "=&r")
	(div:HF (match_operand:HF 1 "register_operand" "r")
		(match_operand:HF 2 "register_operand" "r")))
   (clobber (reg:QI 13))
   (clobber (match_dup 1))
   (clobber (match_dup 2))
   (clobber (match_scratch:QI 3 "=&r"))
   (clobber (match_scratch:QI 4 "=&r"))]
  ""
  "*
{
  if (REGNO (operands [3]) < REGNO (operands [4])) {
    return tsu_fill_delay_slot (1, \"fcall\\tfdiv@%1@%2@%0@%3@%4\");
  } else {
    return tsu_fill_delay_slot (1, \"fcall\\tfdiv@%1@%2@%0@%4@%3\");
  }
}"
  [(set_attr "length" "6")
   (set_attr "type" "t_call")])

(define_insn "tsu_test_double"
  [(set (cc0)
	(match_operand:HF 0 "register_operand" "r"))
   (clobber (match_dup 0))
   (clobber (match_scratch:QI 1 "=&r"))]
  ""
  "*
{
  return (\"\\t\\t; begin ftest\;\"
	  \"test\\t%0_1\;\"
	  \"jnt\\t1f\;\"
	  \"not\\t%0_0, %0_0\;\"
	  \"lshr1\\t%0_0, %0_1\;\"
	  \"zero\\tr15\;\"
	  \"add\\t%0_1, %0_1, r15\\n\"
	  \"1:\;\"
	  \"\\t\\t; end ftest\;\"
	  \"\\t\\t; %1 is free\");
}"
  [(set_attr "length" "6")])

(define_insn "tsu_cmp_double"
  [(set (cc0)
	(compare (match_operand:HF 0 "register_operand" "r")
		 (match_operand:HF 1 "register_operand" "r")))
   (clobber (match_dup 0))
   (clobber (match_dup 1))
   (clobber (reg:QI 13))
   (clobber (match_scratch:QI 2 "=&r"))]
  ""
  "*
{
  return tsu_fill_delay_slot (1,
			      \"\\t\\t; begin fcmp\;\"
			      \"fcall\\tfcmp@%0@%1\;\"
			      \"\\t\\t; end fcmp\;\"
			      \"\\t\\t; %2 is free\");
}"
  [(set_attr "length" "6")
   (set_attr "type" "t_call")])

(define_insn "tsu_w2f_double"
  [(set (match_operand:HF 0 "register_operand" "=&r")
	(float:HF (match_operand:QI 1 "register_operand" "r")))
   (clobber (match_dup 1))
   (clobber (reg:QI 13))]
  ""
  "* return tsu_fill_delay_slot (1, \"fcall\\tw2f@%1@%0\"); "
  [(set_attr "length" "6")
   (set_attr "type" "t_call")])

(define_insn "tsu_f2w_double"
  [(set (match_operand:QI 0 "register_operand" "=&r")
	(fix:QI (fix:HF (match_operand:HF 1 "register_operand" "r"))))
   (clobber (match_dup 1))
   (clobber (reg:QI 13))]
  ""
  "* return tsu_fill_delay_slot (1, \"fcall\\tf2w@%1@%0\"); "
  [(set_attr "length" "6")
   (set_attr "type" "t_call")])

(define_insn "tsu_addr_load_double"
  [(set (match_operand:HF 0 "register_operand" "=r")
	(match_operand:HF 1 "memory_operand" "m"))]
  ""
  "*
{
  if (tsu_base_reg (operands [1]) == REGNO (operands [0]) + 1) {
    return tsu_fill_delay_slot (2,
				\"addr\\t%1.+0\;\"
				\"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\;\"
				\"load\\t%0_0\"
				\"addr\\t%1.+1\;\"
				\"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\;\"
				\"load\\t%0_1\;\");
  } else {
    return tsu_fill_delay_slot (2,
				\"addr\\t%1.+1\;\"
				\"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\;\"
				\"load\\t%0_1\;\"
				\"addr\\t%1.+0\;\"
				\"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\;\"
				\"load\\t%0_0\");
  }
}"
  [(set_attr "type" "t_mem_double")
   (set_attr "length" "6")])

(define_insn "tsu_addr_load_1"
  [(set (strict_low_part (subreg:QI (match_operand:HF 0 "register_operand" "=r")
				    1))
	(subreg:QI (match_operand:HF 1 "memory_operand" "m")
		   1))]
  ""
  "*
{
  return tsu_fill_delay_slot (1,
			      \"addr\\t%1.+1\;\"
			      \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\;\"
			      \"load\\t%0_1\");
}"
  [(set_attr "type" "t_mem")
   (set_attr "length" "3")])

(define_insn "tsu_addr_load_0"
  [(set (strict_low_part (subreg:QI (match_operand:HF 0 "register_operand" "=r")
				    0))
	(subreg:QI (match_operand:HF 1 "memory_operand" "m")
		   0))]
  ""
  "*
{
  return tsu_fill_delay_slot (1,
			      \"addr\\t%1.+0\;\"
			      \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\;\"
			      \"load\\t%0_0\");
}"
  [(set_attr "type" "t_mem")
   (set_attr "length" "3")])

(define_split
  [(set (match_operand:HF 0 "register_operand" "=r")
	(match_operand:HF 1 "memory_operand" "m"))]
  ""
  [(set (match_operand:HF 0 "register_operand" "=r")
	(match_operand:HF 1 "memory_operand" "m"))]
  "
{
  if (tsu_base_reg (operands [1]) == REGNO (operands [0]) + 1) {
    emit_insn (gen_tsu_addr_load_0 (operands [0], operands [1]));
    emit_insn (gen_tsu_addr_load_1 (operands [0], operands [1]));
  } else {
    emit_insn (gen_tsu_addr_load_1 (operands [0], operands [1]));
    emit_insn (gen_tsu_addr_load_0 (operands [0], operands [1]));
  }

  DONE;
}")

(define_insn "tsu_store_double"
  [(set (match_operand:HF 0 "memory_operand" "=m")
	(match_operand:HF 1 "register_operand" "r"))]
  ""
  "*
{
  static char buf [1000];
  rtx exp, exp0, exp1;
  int regno, intval;

  exp = XEXP (operands [0], 0);

  if (GET_CODE (exp) == PLUS) {
    exp0 = XEXP (exp, 0);
    exp1 = XEXP (exp, 1);

    if (GET_CODE (exp0) == CONST_INT) {
      intval = INTVAL (exp0);
      regno = REGNO (exp1);
    } else /* if (GET_CODE (exp1) == CONST_INT) */ {
      regno = REGNO (exp0);
      intval = INTVAL (exp1);
    }

    if (intval + 1 >= 32) {
      sprintf (buf,
	       \"set\\t%d, r15\;\"
	       \"add\\tr15, r%d, r15\;\"
	       \"store\\tr15 + 0.+1, %%1_1\;\"
	       \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\;\"
	       \"set\\t%d, r15\;\"
	       \"add\\tr15, r%d, r15\;\"
	       \"store\\tr15 + 0.+0, %%1_0\;\"
	       \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\",
	       intval,
	       regno,
	       intval,
	       regno);

      return tsu_fill_delay_slot (2, buf);
    }
  }

  return tsu_fill_delay_slot (2,
			      \"store\\t%0.+1, %1_1\;\"
			      \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\;\"
			      \"store\\t%0.+0, %1_0\;\"
			      \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\");
}"
  [(set_attr "type" "t_mem_double")
   (set_attr "length" "10")])

(define_insn "tsu_store_1"
  [(set (strict_low_part (subreg:QI (match_operand:HF 0 "memory_operand" "=m")
				    1))
	(subreg:QI (match_operand:HF 1 "register_operand" "r")
		   1))]
  ""
  "*
{
  static char buf [1000];
  rtx exp, exp0, exp1;
  int regno, intval;

  exp = XEXP (operands [0], 0);

  if (GET_CODE (exp) == PLUS) {
    exp0 = XEXP (exp, 0);
    exp1 = XEXP (exp, 1);

    if (GET_CODE (exp0) == CONST_INT) {
      intval = INTVAL (exp0);
      regno = REGNO (exp1);
    } else /* if (GET_CODE (exp1) == CONST_INT) */ {
      regno = REGNO (exp0);
      intval = INTVAL (exp1);
    }

    if (intval + 1 >= 32) {
      sprintf (buf,
	       \"set\\t%d, r15\;\"
	       \"add\\tr15, r%d, r15\;\"
	       \"store\\tr15 + 0.+1, %%1_1\;\"
	       \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\",
	       intval,
	       regno);

      return tsu_fill_delay_slot (1, buf);
    }
  }

  return tsu_fill_delay_slot (1,
			      \"store\\t%0.+1, %1_1\;\"
			      \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\");
}"
  [(set_attr "type" "t_mem")
   (set_attr "length" "5")])

(define_insn "tsu_store_0"
  [(set (strict_low_part (subreg:QI (match_operand:HF 0 "memory_operand" "=m")
				    0))
	(subreg:QI (match_operand:HF 1 "register_operand" "r")
		   0))]
  ""
  "*
{
  static char buf [1000];
  rtx exp, exp0, exp1;
  int regno, intval;

  exp = XEXP (operands [0], 0);

  if (GET_CODE (exp) == PLUS) {
    exp0 = XEXP (exp, 0);
    exp1 = XEXP (exp, 1);

    if (GET_CODE (exp0) == CONST_INT) {
      intval = INTVAL (exp0);
      regno = REGNO (exp1);
    } else /* if (GET_CODE (exp1) == CONST_INT) */ {
      regno = REGNO (exp0);
      intval = INTVAL (exp1);
    }

    if (intval >= 32) {
      sprintf (buf,
	       \"set\\t%d, r15\;\"
	       \"add\\tr15, r%d, r15\;\"
	       \"store\\tr15 + 0.+0, %%1_0\;\"
	       \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\",
	       intval,
	       regno);

      return tsu_fill_delay_slot (1, buf);
    }
  }

  return tsu_fill_delay_slot (1,
			      \"store\\t%0.+0, %1_0\;\"
			      \"nop\\t\\t; A DELAY_SLOT. REPLACE ME!\");
}"
  [(set_attr "type" "t_mem")
   (set_attr "length" "5")])

(define_split
  [(set (match_operand:HF 0 "memory_operand" "=m")
	(match_operand:HF 1 "register_operand" "r"))]
  ""
  [(set (match_operand:HF 0 "memory_operand" "=m")
	(match_operand:HF 1 "register_operand" "r"))]
  "
{
  emit_insn (gen_tsu_store_1 (operands [0], operands [1]));
  emit_insn (gen_tsu_store_0 (operands [0], operands [1]));
  DONE;
}")

(define_insn "tsu_mov_double"
  [(set (match_operand:HF 0 "register_operand" "=r")
	(match_operand:HF 1 "register_operand" "r"))]
  ""
  "*
{
  if (REGNO (operands [0]) < REGNO (operands [1])) {
    return \"mov\\t%1_0, %0_0\;mov\\t%1_1, %0_1\";
  } else {
    return \"mov\\t%1_1, %0_1\;mov\\t%1_0, %0_0\";
  }
}"
  [(set_attr "length" "2")])

(define_insn "tsu_mov_1"
  [(set (strict_low_part (subreg:QI (match_operand:HF 0 "register_operand" "=r")
				    1))
	(subreg:QI (match_operand:HF 1 "register_operand" "r")
		   1))]
  ""
  "mov\\t%1_1, %0_1")

(define_insn "tsu_mov_0"
  [(set (strict_low_part (subreg:QI (match_operand:HF 0 "register_operand" "=r")
				    0))
	(subreg:QI (match_operand:HF 1 "register_operand" "r")
		   0))]
  ""
  "mov\\t%1_0, %0_0")

(define_split
  [(set (match_operand:HF 0 "register_operand" "=r")
	(match_operand:HF 1 "register_operand" "r"))]
  ""
  [(set (match_operand:HF 0 "register_operand" "=r")
	(match_operand:HF 1 "register_operand" "r"))]
  "
{
  if (REGNO (operands [0]) < REGNO (operands [1])) {
    emit_insn (gen_tsu_mov_0 (operands [0], operands [1]));
    emit_insn (gen_tsu_mov_1 (operands [0], operands [1]));
    DONE;
  } else {
    emit_insn (gen_tsu_mov_1 (operands [0], operands [1]));
    emit_insn (gen_tsu_mov_0 (operands [0], operands [1]));
    DONE;
  }
}")

(define_insn "tsu_set_double"
  [(set (match_operand:HF 0 "register_operand" "=r")
	(match_operand:HF 1 "immediate_operand" "i"))]
  ""
  "set\\t%1.1, %0_1\;set\\t%1.0, %0_0"
  [(set_attr "length" "4")])

(define_insn "tsu_set_1"
  [(set (strict_low_part (subreg:QI (match_operand:HF 0 "register_operand" "=r")
				    1))
	(subreg:QI (match_operand:HF 1 "immediate_operand" "i")
		   1))]
  ""
  "set\\t%1.1, %0_1"
  [(set_attr "length" "2")])

(define_insn "tsu_set_0"
  [(set (strict_low_part (subreg:QI (match_operand:HF 0 "register_operand" "=r")
				    0))
	(subreg:QI (match_operand:HF 1 "immediate_operand" "i")
		   0))]
  ""
  "set\\t%1.0, %0_0"
  [(set_attr "length" "2")])

(define_split
  [(set (match_operand:HF 0 "register_operand" "=r")
	(match_operand:HF 1 "immediate_operand" "i"))]
  ""
  [(set (match_operand:HF 0 "register_operand" "=r")
	(match_operand:HF 1 "immediate_operand" "i"))]
  "
{
  emit_insn (gen_tsu_set_1 (operands [0], operands [1]));
  emit_insn (gen_tsu_set_0 (operands [0], operands [1]));
  DONE;
}")

(define_insn "tsu_neg_double"
  [(set (match_operand:HF 0 "register_operand" "=r")
	(neg:HF (match_operand:HF 1 "register_operand" "r")))]
  ""
  "*
{
  if (REGNO (operands [0]) == REGNO (operands [1])) {
    return \"set\\t1, r15\;xor\\t%1_0, r15, %0_0\";
  } else {
    return \"set\\t1, r15\;mov\\t%1_1, %0_1\;xor\\t%1_0, r15, %0_0\";
  }
}"
  [(set_attr "length" "4")])

(define_insn "tsu_xor_btm"
  [(set (strict_low_part (subreg:QI (match_operand:HF 0 "register_operand" "=r")
				    0))
	(xor:QI (subreg:QI (match_operand:HF 1 "register_operand" "r")
			   0)
		(const_int 1)))]
  ""
  "set\\t1, r15\;xor\\t%1_0, r15, %0_0"
  [(set_attr "length" "3")])

(define_split
  [(set (match_operand:HF 0 "register_operand" "=r")
	(neg:HF (match_operand:HF 1 "register_operand" "r")))]
  ""
  [(set (match_operand:HF 0 "register_operand" "=r")
	(neg:HF (match_operand:HF 1 "register_operand" "r")))]
  "
{
  if (REGNO (operands [0]) != REGNO (operands [1])) {
    emit_insn (gen_tsu_mov_1 (operands [0],
			      operands [1]));
  }

  emit_insn (gen_tsu_xor_btm (operands [0],
			      operands [1]));

  DONE;
}")

(define_insn "tsu_abs_double"
  [(set (match_operand:HF 0 "register_operand" "=r")
	(abs:HF (match_operand:HF 1 "register_operand" "r")))]
  ""
  "*
{
  if (REGNO (operands [0]) == REGNO (operands [1])) {
    return \"shr1\\t%1_0, %0_0\;shl1\\t%0_0, %0_0\";
  } else {
    return \"mov\\t%1_1, %0_1\;shr1\\t%1_0, %0_0\;shl1\\t%0_0, %0_0\";
  }
}"
  [(set_attr "length" "3")])

(define_insn "tsu_shr1_0"
  [(set (strict_low_part (subreg:QI (match_operand:HF 0 "register_operand" "=r")
				    0))
	(lshiftrt:QI (subreg:QI (match_operand:HF 1 "register_operand" "r")
				0)
		     (const_int 1)))]
  ""
  "shr1\\t%1_0, %0_0")

(define_insn "tsu_shl1_0"
  [(set (strict_low_part (subreg:QI (match_operand:HF 0 "register_operand" "=r")
				    0))
	(ashift:QI (subreg:QI (match_operand:HF 1 "register_operand" "r")
			      0)
		   (const_int 1)))]
  ""
  "shl1\\t%1_0, %0_0")

(define_split
  [(set (match_operand:HF 0 "register_operand" "=r")
	(abs:HF (match_operand:HF 1 "register_operand" "r")))]
  ""
  [(set (match_operand:HF 0 "register_operand" "=r")
	(abs:HF (match_operand:HF 1 "register_operand" "r")))]
  "
{
  if (REGNO (operands [0]) != REGNO (operands [1])) {
    emit_insn (gen_tsu_mov_1 (operands [0],
			      operands [1]));
  }

  emit_insn (gen_tsu_shr1_0 (operands [0],
			     operands [1]));
  emit_insn (gen_tsu_shl1_0 (operands [0],
			     operands [0]));

  DONE;
}")

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

(define_expand "nop"
  [(const_int 0)]
  ""
  "
{
  emit_insn (gen_tsu_nop ());
  DONE;
}")

(define_expand "movqi"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(match_operand:QI 1 "general_operand" "g"))]
  ""
  "
{
  if (register_operand (operands [0], QImode)) {
    if (register_operand (operands [1], QImode)) {
      emit_insn (gen_tsu_mov (operands [0],
			      operands [1]));
      DONE;
    } else if (immediate_operand (operands [1], QImode)) {
      if (operands [1] == const0_rtx) {
        emit_insn (gen_tsu_zero (operands [0]));
	DONE;
      } else {
        emit_insn (gen_tsu_set (operands [0],
				operands [1]));
        DONE;
      }
    } else {
      emit_insn (gen_tsu_addr_load (operands [0],
				    operands [1]));
      DONE;
    }
  } else if (immediate_operand (operands [0], QImode)) {
    abort ();
  } else {
    if (register_operand (operands [1], QImode)) {
      emit_insn (gen_tsu_store (operands [0],
				operands [1]));
      DONE;
    } else if (immediate_operand (operands [1], QImode)) {
      rtx tmp;
      tmp = gen_reg_rtx (QImode);
      emit_insn (gen_tsu_set (tmp,
			      operands [1]));
      emit_insn (gen_tsu_store (operands [0],
				tmp));
      DONE;
    } else {
      rtx tmp;
      tmp = gen_reg_rtx (QImode);
      emit_insn (gen_tsu_addr_load (tmp,
				    operands [1]));
      emit_insn (gen_tsu_store (operands [0],
				tmp));
      DONE;
    }
  }
}")

(define_expand "andqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(and:QI (match_operand:QI 1 "register_operand" "%r")
		(match_operand:QI 2 "register_operand" "r")))]
  ""
  "
{
  emit_insn (gen_tsu_and (operands [0],
			  operands [1],
			  operands [2]));
  DONE;
}")

(define_expand "iorqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(ior:QI (match_operand:QI 1 "register_operand" "%r")
		(match_operand:QI 2 "register_operand" "r")))]
  ""
  "
{
  emit_insn (gen_tsu_or (operands [0],
			 operands [1],
			 operands [2]));
  DONE;
}")

(define_expand "xorqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(xor:QI (match_operand:QI 1 "register_operand" "%r")
		(match_operand:QI 2 "register_operand" "r")))]
  ""
  "
{
  emit_insn (gen_tsu_xor (operands [0],
			  operands [1],
			  operands [2]));
  DONE;
}")

(define_expand "one_cmplqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(not:QI (match_operand:QI 1 "register_operand" "r")))]
  ""
  "
{
  emit_insn (gen_tsu_not (operands [0],
			  operands [1]));
  DONE;
}")

(define_expand "addqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(plus:QI (match_operand:QI 1 "general_operand" "%g")
		 (match_operand:QI 2 "general_operand" "g")))]
  ""
  "
{
  if (register_operand (operands [1], QImode)) {
    if (register_operand (operands [2], QImode)) {
      emit_insn (gen_tsu_add (operands [0],
			      operands [1],
			      operands [2]));
      DONE;
    } else if (immediate_operand (operands [2], QImode)) {
      rtx tmp;

      if (GET_CODE (operands [2]) == CONST_INT) {
        switch (INTVAL (operands [2])) {
        case 1:
          emit_insn (gen_tsu_add1 (operands [0],
				   operands [1]));
          DONE;
	case 2:
	  emit_insn (gen_tsu_add1 (operands [0],
				   operands [1]));
	  emit_insn (gen_tsu_add1 (operands [0],
				   operands [0]));
	  DONE;
	case -1:
	  emit_insn (gen_tsu_sub1 (operands [0],
				   operands [1]));
	  DONE;
	case -2:
	  emit_insn (gen_tsu_sub1 (operands [0],
				   operands [1]));
	  emit_insn (gen_tsu_sub1 (operands [0],
				   operands [0]));
	  DONE;
	}
      }

      tmp = gen_reg_rtx (QImode);
      emit_insn (gen_tsu_set (tmp,
			      operands [2]));
      emit_insn (gen_tsu_add (operands [0],
			      operands [1],
			      tmp));
      DONE;
    } else {
      rtx tmp;
      tmp = gen_reg_rtx (QImode);
      emit_insn (gen_tsu_addr_load (tmp,
				    operands [2]));
      emit_insn (gen_tsu_add (operands [0],
			      operands [1],
			      tmp));
      DONE;
    }
  } else if (immediate_operand (operands [1], QImode)) {
    if (register_operand (operands [2], QImode)) {
      rtx tmp;

      if (GET_CODE (operands [1]) == CONST_INT) {
        switch (INTVAL (operands [1])) {
        case 1:
          emit_insn (gen_tsu_add1 (operands [0],
				   operands [2]));
          DONE;
	case 2:
	  emit_insn (gen_tsu_add1 (operands [0],
				   operands [2]));
	  emit_insn (gen_tsu_add1 (operands [0],
				   operands [0]));
	  DONE;
	case -1:
	  emit_insn (gen_tsu_sub1 (operands [0],
				   operands [2]));
	  DONE;
	case -2:
	  emit_insn (gen_tsu_sub1 (operands [0],
				   operands [2]));
	  emit_insn (gen_tsu_sub1 (operands [0],
				   operands [0]));
	  DONE;
	}
      }

      tmp = gen_reg_rtx (QImode);
      emit_insn (gen_tsu_set (tmp,
			      operands [1]));
      emit_insn (gen_tsu_add (operands [0],
			      tmp,
			      operands [2]));
      DONE;
    } else if (immediate_operand (operands [2], QImode)) {
      abort ();
    } else {
      rtx tmp1, tmp2;
      tmp1 = gen_reg_rtx (QImode);
      emit_insn (gen_tsu_set (tmp1,
			      operands [1]));
      tmp2 = gen_reg_rtx (QImode);
      emit_insn (gen_tsu_addr_load (tmp2,
				    operands [2]));
      emit_insn (gen_tsu_add (operands [0],
			      tmp1,
			      tmp2));
      DONE;
    }
  } else {
    if (register_operand (operands [2], QImode)) {
      rtx tmp;
      tmp = gen_reg_rtx (QImode);
      emit_insn (gen_tsu_addr_load (tmp,
				    operands [1]));
      emit_insn (gen_tsu_add (operands [0],
			      tmp,
			      operands [2]));
      DONE;
    } else if (immediate_operand (operands [2], QImode)) {
      rtx tmp1, tmp2;
      tmp1 = gen_reg_rtx (QImode);
      emit_insn (gen_tsu_addr_load (tmp1,
				    operands [1]));
      tmp2 = gen_reg_rtx (QImode);
      emit_insn (gen_tsu_set (tmp2,
			      operands [1]));
      emit_insn (gen_tsu_add (operands [0],
			      tmp1,
			      tmp2));
      DONE;
    } else {
      rtx tmp1, tmp2;
      tmp1 = gen_reg_rtx (QImode);
      emit_insn (gen_tsu_addr_load (tmp1,
				    operands [1]));
      tmp2 = gen_reg_rtx (QImode);
      emit_insn (gen_tsu_addr_load (tmp2,
				    operands [2]));
      emit_insn (gen_tsu_add (operands [0],
			      tmp1,
			      tmp2));
      DONE;
    }
  }
}")

(define_expand "subqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(minus:QI (match_operand:QI 1 "register_operand" "r")
		  (match_operand:QI 2 "register_operand" "r")))]
  ""
  "
{
  emit_insn (gen_tsu_sub (operands [0],
			  operands [1],
			  operands [2]));
  DONE;
}")

(define_expand "mulqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(mult:QI (match_operand:QI 1 "register_operand" "%r")
		 (match_operand:QI 2 "register_operand" "r")))]
  ""
  "
{
  rtx tmp0, tmp1, tmp2, tmp3;

  tmp0 = gen_reg_rtx (QImode);
  tmp1 = gen_reg_rtx (QImode);
  tmp2 = gen_reg_rtx (QImode);
  tmp3 = gen_reg_rtx (QImode);

  /* mov %1, tmp1 */
  emit_insn (gen_tsu_mov (tmp1,
			  operands [1]));
  /* mov %2, tmp2 */
  emit_insn (gen_tsu_mov (tmp2,
			  operands [2]));

  /* mulhl tmp1, tmp2 */
  /* load tmp0 */
  emit_insn (gen_tsu_mulhl_load (tmp0,
				 tmp1,
				 tmp2));
  /* mullh tmp1, tmp2 */
  /* load tmp3 */
  emit_insn (gen_tsu_mullh_load (tmp3,
				 tmp1,
				 tmp2));
  /* add tmp0, tmp3, tmp0 */
  emit_insn (gen_tsu_add (tmp0,
			  tmp3,
			  tmp0));
  /* zero tmp3 */
  emit_insn (gen_tsu_zero (tmp3));
  /* getll1 tmp0, tmp3 */
  emit_insn (gen_tsu_getll (tmp0,
			    tmp0,
			    tmp3));
  /* mulll tmp1, tmp2 */
  /* load tmp3 */
  emit_insn (gen_tsu_mulll_load (tmp3,
				 tmp1,
				 tmp2));
  /* add tmp0, tmp3, tmp0 */
  emit_insn (gen_tsu_add (tmp0,
			  tmp3,
			  tmp0));

  /* mov tmp0, %0 */
  emit_insn (gen_tsu_mov (operands [0],
			  tmp0));

  DONE;
}")

(define_expand "divmodqi4"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(div:QI (match_operand:QI 1 "register_operand" "r")
		(match_operand:QI 2 "register_operand" "r")))
   (set (match_operand:QI 3 "register_operand" "=r")
	(mod:QI (match_dup 1)
		(match_dup 2)))]
  ""
  "
{
  rtx tmp, r0, r1, fun;

  tmp = gen_reg_rtx (QImode);

  r0 = gen_rtx (REG,
		QImode,
		0);
  r1 = gen_rtx (REG,
		QImode,
		1);

  fun = gen_rtx (SYMBOL_REF,
		 QImode,
		 \"__divmodqi4\");

  emit_insn (gen_tsu_mov (tmp,
			  operands [2]));
  emit_insn (gen_tsu_mov (r0,
			  operands [1]));
  emit_insn (gen_tsu_mov (r1,
			  tmp));

  emit_insn (gen_rtx (USE,
		      VOIDmode,
		      r0));
  emit_insn (gen_rtx (USE,
		      VOIDmode,
		      r1));

  emit_call_insn (gen_tsu_call_value_imm (fun,
					  const0_rtx));

  emit_insn (gen_tsu_mov (tmp,
			  r0));
  emit_insn (gen_tsu_mov (operands [3],
			  r1));
  emit_insn (gen_tsu_mov (operands [0],
			  tmp));

  DONE;
}")

(define_expand "divqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(div:QI (match_operand:QI 1 "register_operand" "r")
		(match_operand:QI 2 "register_operand" "r")))]
  ""
  "
{
  rtx tmp, r0, r1, fun;

  tmp = gen_reg_rtx (QImode);

  r0 = gen_rtx (REG,
		QImode,
		0);
  r1 = gen_rtx (REG,
		QImode,
		1);

  fun = gen_rtx (SYMBOL_REF,
		 QImode,
		 \"__divqi3\");

  emit_insn (gen_tsu_mov (tmp,
			  operands [2]));
  emit_insn (gen_tsu_mov (r0,
			  operands [1]));
  emit_insn (gen_tsu_mov (r1,
			  tmp));

  emit_insn (gen_rtx (USE,
		      VOIDmode,
		      r0));
  emit_insn (gen_rtx (USE,
		      VOIDmode,
		      r1));

  emit_call_insn (gen_tsu_call_value_imm (fun,
					  const0_rtx));

  emit_insn (gen_tsu_mov (operands [0],
			  r0));

  DONE;
}")

(define_expand "modqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(mod:QI (match_operand:QI 1 "register_operand" "r")
		(match_operand:QI 2 "register_operand" "r")))]
  ""
  "
{
  rtx tmp, r0, r1, ref, fun;

  tmp = gen_reg_rtx (QImode);

  r0 = gen_rtx (REG,
		QImode,
		0);
  r1 = gen_rtx (REG,
		QImode,
		1);

  fun = gen_rtx (SYMBOL_REF,
		 QImode,
		 \"__modqi3\");

  emit_insn (gen_tsu_mov (tmp,
			  operands [2]));
  emit_insn (gen_tsu_mov (r0,
			  operands [1]));
  emit_insn (gen_tsu_mov (r1,
			  tmp));

  emit_insn (gen_rtx (USE,
		      VOIDmode,
		      r0));
  emit_insn (gen_rtx (USE,
		      VOIDmode,
		      r1));

  emit_call_insn (gen_tsu_call_value_imm (fun,
					  const0_rtx));

  emit_insn (gen_tsu_mov (operands [0],
			  r0));

  DONE;
}")

(define_expand "udivmodqi4"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(udiv:QI (match_operand:QI 1 "register_operand" "r")
		 (match_operand:QI 2 "register_operand" "r")))
   (set (match_operand:QI 3 "register_operand" "=r")
	(umod:QI (match_dup 1)
		 (match_dup 2)))]
  ""
  "
{
  rtx tmp, r0, r1, ref, fun;

  tmp = gen_reg_rtx (QImode);

  r0 = gen_rtx (REG,
		QImode,
		0);
  r1 = gen_rtx (REG,
		QImode,
		1);

  fun = gen_rtx (SYMBOL_REF,
		 QImode,
		 \"__udivmodqi4\");

  emit_insn (gen_tsu_mov (tmp,
			  operands [2]));
  emit_insn (gen_tsu_mov (r0,
			  operands [1]));
  emit_insn (gen_tsu_mov (r1,
			  tmp));

  emit_insn (gen_rtx (USE,
		      VOIDmode,
		      r0));
  emit_insn (gen_rtx (USE,
		      VOIDmode,
		      r1));

  emit_call_insn (gen_tsu_call_value_imm (fun,
					  const0_rtx));

  emit_insn (gen_tsu_mov (tmp,
			  r0));
  emit_insn (gen_tsu_mov (operands [3],
			  r1));
  emit_insn (gen_tsu_mov (operands [0],
			  tmp));

  DONE;
}")

(define_expand "udivqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(udiv:QI (match_operand:QI 1 "register_operand" "r")
		 (match_operand:QI 2 "register_operand" "r")))]
  ""
  "
{
  rtx tmp, r0, r1, ref, fun;

  tmp = gen_reg_rtx (QImode);

  r0 = gen_rtx (REG,
		QImode,
		0);
  r1 = gen_rtx (REG,
		QImode,
		1);

  fun = gen_rtx (SYMBOL_REF,
		 QImode,
		 \"__udivqi3\");

  emit_insn (gen_tsu_mov (tmp,
			  operands [2]));
  emit_insn (gen_tsu_mov (r0,
			  operands [1]));
  emit_insn (gen_tsu_mov (r1,
			  tmp));

  emit_insn (gen_rtx (USE,
		      VOIDmode,
		      r0));
  emit_insn (gen_rtx (USE,
		      VOIDmode,
		      r1));

  emit_call_insn (gen_tsu_call_value_imm (fun,
					  const0_rtx));

  emit_insn (gen_tsu_mov (operands [0],
			  r0));

  DONE;
}")

(define_expand "umodqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(umod:QI (match_operand:QI 1 "register_operand" "r")
		 (match_operand:QI 2 "register_operand" "r")))]
  ""
  "
{
  rtx tmp, r0, r1, ref, fun;

  tmp = gen_reg_rtx (QImode);

  r0 = gen_rtx (REG,
		QImode,
		0);
  r1 = gen_rtx (REG,
		QImode,
		1);

  fun = gen_rtx (SYMBOL_REF,
		 QImode,
		 \"__umodqi3\");

  emit_insn (gen_tsu_mov (tmp,
			  operands [2]));
  emit_insn (gen_tsu_mov (r0,
			  operands [1]));
  emit_insn (gen_tsu_mov (r1,
			  tmp));

  emit_insn (gen_rtx (USE,
		      VOIDmode,
		      r0));
  emit_insn (gen_rtx (USE,
		      VOIDmode,
		      r1));

  emit_call_insn (gen_tsu_call_value_imm (fun,
					  const0_rtx));

  emit_insn (gen_tsu_mov (operands [0],
			  r0));

  DONE;
}")

(define_expand "negqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(neg:QI (match_operand:QI 1 "register_operand" "r")))]
  ""
  "
{
  emit_insn (gen_tsu_neg (operands [0], operands [1]));
  DONE;
}")

(define_expand "absqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(abs:QI (match_operand:QI 1 "register_operand" "r")))]
  ""
  "
{
  emit_insn (gen_tsu_abs (operands [0],
			  operands [1]));
  DONE;
}")

(define_expand "lshrqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(lshiftrt:QI (match_operand:QI 1 "register_operand" "r")
		     (match_operand:QI 2 "general_operand" "g")))]
  ""
  "
{
  rtx tmp, r0, r1, ref, fun;

  if (register_operand (operands [2], QImode)) {
    tmp = gen_reg_rtx (QImode);
    
    r0 = gen_rtx (REG,
		  QImode,
		  0);
    r1 = gen_rtx (REG,
		  QImode,
		  1);
    
    fun = gen_rtx (SYMBOL_REF,
		   QImode,
		   \"__lshrqi3\");
    
    emit_insn (gen_tsu_mov (tmp,
			    operands [2]));
    emit_insn (gen_tsu_mov (r0,
			    operands [1]));
    emit_insn (gen_tsu_mov (r1,
			    tmp));
    
    emit_insn (gen_rtx (USE,
			VOIDmode,
			r0));
    emit_insn (gen_rtx (USE,
			VOIDmode,
			r1));
    
    emit_call_insn (gen_tsu_call_value_imm (fun,
					    const0_rtx));
    
    emit_insn (gen_tsu_mov (operands [0],
			    r0));
    
    DONE;
  } else if (immediate_operand (operands [2], QImode)) {
    if (GET_CODE (operands [2]) == CONST_INT) {
      switch (INTVAL (operands [2])) {
      case 1:
	emit_insn (gen_tsu_shr1 (operands [0],
				 operands [1]));
	DONE;
      case 2:
	emit_insn (gen_tsu_shr2 (operands [0],
				 operands [1]));
	DONE;
      }
    }

    tmp = gen_reg_rtx (QImode);
    
    r0 = gen_rtx (REG,
		  QImode,
		  0);
    r1 = gen_rtx (REG,
		  QImode,
		  1);
    
    fun = gen_rtx (SYMBOL_REF,
		   QImode,
		   \"__lshrqi3\");
    
    emit_insn (gen_tsu_set (tmp,
			    operands [2]));
    emit_insn (gen_tsu_mov (r0,
			    operands [1]));
    emit_insn (gen_tsu_mov (r1,
			    tmp));
    
    emit_insn (gen_rtx (USE,
			VOIDmode,
			r0));
    emit_insn (gen_rtx (USE,
			VOIDmode,
			r1));
    
    emit_call_insn (gen_tsu_call_value_imm (fun,
					    const0_rtx));
    
    emit_insn (gen_tsu_mov (operands [0],
			    r0));
    
    DONE;
  } else {
    tmp = gen_reg_rtx (QImode);
    
    r0 = gen_rtx (REG,
		  QImode,
		  0);
    r1 = gen_rtx (REG,
		  QImode,
		  1);
    
    fun = gen_rtx (SYMBOL_REF,
		   QImode,
		   \"__lshrqi3\");
    
    emit_insn (gen_tsu_addr_load (tmp,
				  operands [2]));
    emit_insn (gen_tsu_mov (r0,
			    operands [1]));
    emit_insn (gen_tsu_mov (r1,
			    tmp));
    
    emit_insn (gen_rtx (USE,
			VOIDmode,
			r0));
    emit_insn (gen_rtx (USE,
			VOIDmode,
			r1));
    
    emit_call_insn (gen_tsu_call_value_imm (fun,
					    const0_rtx));
    
    emit_insn (gen_tsu_mov (operands [0],
			    r0));
    
    DONE;
  }
}")

(define_expand "ashrqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(ashiftrt:QI (match_operand:QI 1 "register_operand" "r")
		     (match_operand:QI 2 "register_operand" "r")))]
  ""
  "
{
  rtx tmp, r0, r1, ref, fun;

  tmp = gen_reg_rtx (QImode);

  r0 = gen_rtx (REG,
		QImode,
		0);
  r1 = gen_rtx (REG,
		QImode,
		1);

  fun = gen_rtx (SYMBOL_REF,
		 QImode,
		 \"__ashrqi3\");

  emit_insn (gen_tsu_mov (tmp,
			  operands [2]));
  emit_insn (gen_tsu_mov (r0,
			  operands [1]));
  emit_insn (gen_tsu_mov (r1,
			  tmp));

  emit_insn (gen_rtx (USE,
		      VOIDmode,
		      r0));
  emit_insn (gen_rtx (USE,
		      VOIDmode,
		      r1));

  emit_call_insn (gen_tsu_call_value_imm (fun,
					  const0_rtx));

  emit_insn (gen_tsu_mov (operands [0],
			  r0));

  DONE;
}")

(define_expand "ashlqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(ashift:QI (match_operand:QI 1 "register_operand" "r")
		   (match_operand:QI 2 "general_operand" "g")))]
  ""
  "
{
  rtx tmp, r0, r1, ref, fun;

  if (register_operand (operands [2], QImode)) {
    tmp = gen_reg_rtx (QImode);
    
    r0 = gen_rtx (REG,
		  QImode,
		  0);
    r1 = gen_rtx (REG,
		  QImode,
		  1);
    
    fun = gen_rtx (SYMBOL_REF,
		   QImode,
		   \"__ashlqi3\");
    
    emit_insn (gen_tsu_mov (tmp,
			    operands [2]));
    emit_insn (gen_tsu_mov (r0,
			    operands [1]));
    emit_insn (gen_tsu_mov (r1,
			    tmp));
    
    emit_insn (gen_rtx (USE,
			VOIDmode,
			r0));
    emit_insn (gen_rtx (USE,
			VOIDmode,
			r1));
    
    emit_call_insn (gen_tsu_call_value_imm (fun,
					    const0_rtx));
    
    emit_insn (gen_tsu_mov (operands [0],
			    r0));
    
    DONE;
  } else if (immediate_operand (operands [2], QImode)) {
    if (GET_CODE (operands [2]) == CONST_INT) {
      switch (INTVAL (operands [2])) {
      case 1:
	emit_insn (gen_tsu_shl1 (operands [0],
				 operands [1]));
	DONE;
      case 2:
	emit_insn (gen_tsu_shl2 (operands [0],
				 operands [1]));
	DONE;
      }
    }

    tmp = gen_reg_rtx (QImode);
    
    r0 = gen_rtx (REG,
		  QImode,
		  0);
    r1 = gen_rtx (REG,
		  QImode,
		  1);
    
    fun = gen_rtx (SYMBOL_REF,
		   QImode,
		   \"__ashlqi3\");
    
    emit_insn (gen_tsu_set (tmp,
			    operands [2]));
    emit_insn (gen_tsu_mov (r0,
			    operands [1]));
    emit_insn (gen_tsu_mov (r1,
			    tmp));
    
    emit_insn (gen_rtx (USE,
			VOIDmode,
			r0));
    emit_insn (gen_rtx (USE,
			VOIDmode,
			r1));
    
    emit_call_insn (gen_tsu_call_value_imm (fun,
					    const0_rtx));
    
    emit_insn (gen_tsu_mov (operands [0],
			    r0));
    
    DONE;
  } else {
    tmp = gen_reg_rtx (QImode);
    
    r0 = gen_rtx (REG,
		  QImode,
		  0);
    r1 = gen_rtx (REG,
		  QImode,
		  1);
    
    fun = gen_rtx (SYMBOL_REF,
		   QImode,
		   \"__ashlqi3\");
    
    emit_insn (gen_tsu_addr_load (tmp,
				  operands [2]));
    emit_insn (gen_tsu_mov (r0,
			    operands [1]));
    emit_insn (gen_tsu_mov (r1,
			    tmp));
    
    emit_insn (gen_rtx (USE,
			VOIDmode,
			r0));
    emit_insn (gen_rtx (USE,
			VOIDmode,
			r1));
    
    emit_call_insn (gen_tsu_call_value_imm (fun,
					    const0_rtx));
    
    emit_insn (gen_tsu_mov (operands [0],
			    r0));
    
    DONE;
  }
}")

(define_expand "tstqi"
  [(parallel [(set (cc0)
		   (match_operand:QI 0 "register_operand" "r"))
	      (clobber (match_scratch:QI 1 "=&r"))])]
  ""
  "")

(define_expand "cmpqi"
  [(parallel [(set (cc0)
		   (compare (match_operand:QI 0 "register_operand" "r")
			    (match_operand:QI 1 "register_operand" "r")))
	      (clobber (match_scratch:QI 2 "=&r"))])]
  ""
  "")

(define_expand "jump"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
  "
{
  emit_jump_insn (gen_tsu_rj (operands [0]));
  DONE;
}")

(define_expand "indirect_jump"
  [(set (pc)
	(match_operand:QI 0 "register_operand" "r"))]
  ""
  "
{
  emit_jump_insn (gen_tsu_aj (operands [0]));
  DONE;
}")

(define_expand "tablejump"
  [(set (pc)
	(match_operand:QI 0 "register_operand" "r"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "
{
  emit_insn  (gen_tsu_tablejump (operands [0],
				 operands [1]));
  DONE;
}")

(define_expand "call"
  [(call (match_operand:QI 0 "memory_operand" "m")
	 (match_operand 1 "" ""))]
  ""
  "
{
  rtx val, tmp;

  val = XEXP (operands [0], 0);

  if (CONSTANT_P (val)) {
    emit_call_insn (gen_tsu_call_value_imm (val,
					    operands [1]));
  } else {
    val = force_reg (QImode, val);
    emit_call_insn (gen_tsu_call_value (val,
					operands [1]));
  }

  DONE;
}")

(define_expand "call_value"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(call (match_operand:QI 1 "memory_operand" "m")
	      (match_operand 2 "" "")))]
  ""
  "
{
  rtx val, tmp;

  if (REGNO (operands [0]) != 0) {
    abort ();
  }

  val = XEXP (operands [1], 0);

  if (CONSTANT_P (val)) {
    emit_call_insn (gen_tsu_call_value_imm (val,
					    operands [1]));
  } else {
    val = force_reg (QImode, val);
    emit_call_insn (gen_tsu_call_value (val,
					operands [1]));
  }

  DONE;
}")

(define_expand "beq"
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  emit_jump_insn (gen_tsu_rjeq (operands [0]));
  DONE;
}")

(define_expand "bne"
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  emit_jump_insn (gen_tsu_rjne (operands [0]));
  DONE;
}")

(define_expand "bgtu"
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  emit_jump_insn (gen_tsu_rjgtu (operands [0]));
  DONE;
}")

(define_expand "bltu"
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  emit_jump_insn (gen_tsu_rjltu (operands [0]));
  DONE;
}")

(define_expand "bgeu"
  [(set (pc)
	(if_then_else (geu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  emit_jump_insn (gen_tsu_rjgeu (operands [0]));
  DONE;
}")

(define_expand "bleu"
  [(set (pc)
	(if_then_else (leu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  emit_jump_insn (gen_tsu_rjleu (operands [0]));
  DONE;
}")

(define_expand "bgt"
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  emit_jump_insn (gen_tsu_rjgt (operands [0]));
  DONE;
}")

(define_expand "blt"
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  emit_jump_insn (gen_tsu_rjlt (operands [0]));
  DONE;
}")

(define_expand "bge"
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  emit_jump_insn (gen_tsu_rjge (operands [0]));
  DONE;
}")

(define_expand "ble"
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  emit_jump_insn (gen_tsu_rjle (operands [0]));
  DONE;
}")

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

(define_expand "movhf"
  [(set (match_operand:HF 0 "general_operand" "=g")
	(match_operand:HF 1 "general_operand" "g"))]
  ""
  "
{
  if (register_operand (operands [0], HFmode)) {
    if (register_operand (operands [1], HFmode)) {
      emit_insn (gen_tsu_mov_double (operands [0],
				     operands [1]));
      DONE;
    } else if (immediate_operand (operands [1], HFmode)) {
      emit_insn (gen_tsu_set_double (operands [0],
				     operands [1]));
      DONE;
    } else {
      emit_insn (gen_tsu_addr_load_double (operands [0],
					   operands [1]));
      DONE;
    }
  } else if (immediate_operand (operands [0], HFmode)) {
    abort ();
  } else {
    if (register_operand (operands [1], HFmode)) {
      emit_insn (gen_tsu_store_double (operands [0],
				       operands [1]));
      DONE;
    } else if (immediate_operand (operands [1], HFmode)) {
      rtx tmp;
      tmp = gen_reg_rtx (HFmode);
      emit_insn (gen_tsu_set_double (tmp,
				     operands [1]));
      emit_insn (gen_tsu_store_double (operands [0],
				       tmp));
      DONE;
    } else {
      rtx tmp;
      tmp = gen_reg_rtx (HFmode);
      emit_insn (gen_tsu_addr_load_double (tmp,
					   operands [1]));
      emit_insn (gen_tsu_store_double (operands [0],
				       tmp));
      DONE;
    }
  }
}")

(define_expand "addhf3"
  [(set (match_operand:HF 0 "register_operand" "=r")
	(plus:HF (match_operand:HF 1 "register_operand" "%r")
		 (match_operand:HF 2 "register_operand" "r")))]
  ""
  "
{
  rtx src1, src2;

  if (tsu_same_register (operands [1], operands [2])) {
    src1 = gen_reg_rtx (HFmode);
    emit_insn (gen_tsu_mov_double (src1,
				   operands [1]));
    emit_insn (gen_tsu_dbl_double (operands [0],
				   src1));
    DONE;
  }

  src1 = gen_reg_rtx (HFmode);
  src2 = gen_reg_rtx (HFmode);

  emit_insn (gen_tsu_mov_double (src1,
				 operands [1]));
  emit_insn (gen_tsu_mov_double (src2,
				 operands [2]));

  emit_insn (gen_tsu_add_double (operands [0],
				 src1,
				 src2));

  DONE;
}")

(define_expand "subhf3"
  [(set (match_operand:HF 0 "register_operand" "=r")
	(plus:HF (match_operand:HF 1 "register_operand" "r")
		 (match_operand:HF 2 "register_operand" "r")))]
  ""
  "
{
  rtx src1, src2;

  if (tsu_same_register (operands [1], operands [2])) {
    emit_insn (gen_tsu_set_double (operands [0],
				   CONST0_RTX (HFmode)));
    DONE;
  }

  src1 = gen_reg_rtx (HFmode);
  src2 = gen_reg_rtx (HFmode);

  emit_insn (gen_tsu_mov_double (src1,
				 operands [1]));
  emit_insn (gen_tsu_neg_double (src2,
				 operands [2]));

  emit_insn (gen_tsu_add_double (operands [0],
				 src1,
				 src2));

  DONE;
}")

(define_expand "mulhf3"
  [(set (match_operand:HF 0 "register_operand" "=r")
	(plus:HF (match_operand:HF 1 "register_operand" "%r")
		 (match_operand:HF 2 "register_operand" "r")))]
  ""
  "
{
  rtx src1, src2;

  if (tsu_same_register (operands [1], operands [2])) {
    src1 = gen_reg_rtx (HFmode);
    emit_insn (gen_tsu_mov_double (src1,
				   operands [1]));
    emit_insn (gen_tsu_sq_double (operands [0],
				  src1));
    DONE;
  }

  src1 = gen_reg_rtx (HFmode);
  src2 = gen_reg_rtx (HFmode);

  emit_insn (gen_tsu_mov_double (src1,
				 operands [1]));
  emit_insn (gen_tsu_mov_double (src2,
				 operands [2]));

  emit_insn (gen_tsu_mul_double (operands [0],
				 src1,
				 src2));

  DONE;
}")

(define_expand "divhf3"
  [(set (match_operand:HF 0 "register_operand" "=r")
	(plus:HF (match_operand:HF 1 "register_operand" "r")
		 (match_operand:HF 2 "register_operand" "r")))]
  ""
  "
{
  rtx src1, src2;

  if (tsu_same_register (operands [1], operands [2])) {
    emit_insn (gen_tsu_set_double (operands [0],
				   CONST1_RTX (HFmode)));
    DONE;
  }

  src1 = gen_reg_rtx (HFmode);
  src2 = gen_reg_rtx (HFmode);

  emit_insn (gen_tsu_mov_double (src1,
				 operands [1]));
  emit_insn (gen_tsu_mov_double (src2,
				 operands [2]));

  emit_insn (gen_tsu_div_double (operands [0],
				 src1,
				 src2));

  DONE;
}")

(define_expand "tsthf"
  [(set (cc0)
	(match_operand:HF 0 "register_operand" "r"))]
  ""
  "
{
  rtx src;
  src = gen_reg_rtx (HFmode);
  emit_insn (gen_tsu_mov_double (src,
				 operands [0]));
  emit_insn (gen_tsu_test_double (src));
  DONE;
}")

(define_expand "cmphf"
  [(set (cc0)
	(compare (match_operand:HF 0 "register_operand" "r")
		 (match_operand:HF 1 "register_operand" "r")))]
  ""
  "
{
  rtx src1, src2;

  src1 = gen_reg_rtx (HFmode);
  src2 = gen_reg_rtx (HFmode);

  emit_insn (gen_tsu_mov_double (src1,
				 operands [0]));
  emit_insn (gen_tsu_mov_double (src2,
				 operands [1]));

  emit_insn (gen_tsu_cmp_double (src1,
				 src2));

  DONE;
}")

(define_expand "neghf2"
  [(set (match_operand:HF 0 "register_operand" "=r")
	(neg:HF (match_operand:HF 1 "register_operand" "r")))]
  ""
  "
{
  rtx src;
  src = gen_reg_rtx (HFmode);
  emit_insn (gen_tsu_mov_double (src,
				 operands [1]));
  emit_insn (gen_tsu_neg_double (operands [0],
				 src));
  DONE;
}")

(define_expand "abshf2"
  [(set (match_operand:HF 0 "register_operand" "=r")
	(abs:HF (match_operand:HF 1 "register_operand" "r")))]
  ""
  "
{
  rtx src;
  src = gen_reg_rtx (HFmode);
  emit_insn (gen_tsu_mov_double (src,
				 operands [1]));
  emit_insn (gen_tsu_abs_double (operands [0],
				 src));
  DONE;
}")

(define_expand "floatqihf2"
  [(set (match_operand:HF 0 "register_operand" "=r")
	(float:HF (match_operand:QI 1 "register_operand" "r")))]
  ""
  "
{
  rtx src;
  src = gen_reg_rtx (QImode);
  emit_insn (gen_tsu_mov_double (src,
				 operands [1]));
  emit_insn (gen_tsu_w2f_double (operands [0],
				 src));
  DONE;
}")

(define_expand "fix_trunchfqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(fix:QI (fix:HF (match_operand:HF 1 "register_operand" "r"))))]
  ""
  "
{
  rtx src;
  src = gen_reg_rtx (HFmode);
  emit_insn (gen_tsu_mov_double (src,
				 operands [1]));
  emit_insn (gen_tsu_f2w_double (operands [0],
				 src));
  DONE;
}")

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

(define_peephole
  [(set (match_operand 0 "register_operand" "=r")
	(match_operand 1 "register_operand" "r"))
   (set (match_dup 0)
	(match_operand 2 "" ""))]
  ""
  "*
{
  extern int optimize;
  rtx tmp;

  tmp = make_insn_raw (gen_rtx (SET,
				VOIDmode,
				operands [0],
				replace_rtx (copy_rtx (operands [2]),
					     operands [0],
					     operands [1])));

  final_scan_insn (tmp, asm_out_file, optimize, 0, 1);

  return \"\";
}"
  [(set_attr "length" "0")])

(define_peephole
  [(set (match_operand 0 "register_operand" "=r")
	(match_operand 1 "register_operand" "r"))
   (parallel [(set (match_dup 0)
		   (match_operand 2 "" ""))
	      (clobber (match_operand 3 "" ""))])]
  ""
  "*
{
  extern int optimize;
  rtx tmp;

  tmp = make_insn_raw (gen_rtx (SET,
				VOIDmode,
				operands [0],
				replace_rtx (copy_rtx (operands [2]),
					     operands [0],
					     operands [1])));

  final_scan_insn (tmp, asm_out_file, optimize, 0, 1);

  return \"\";
}"
  [(set_attr "length" "0")])

(define_peephole
  [(set (match_operand 0 "register_operand" "=r")
	(match_operand 1 "register_operand" "r"))
   (parallel [(set (match_dup 0)
		   (match_operand 2 "" ""))
	      (clobber (match_operand 3 "" ""))
	      (clobber (match_operand 4 "" ""))])]
  ""
  "*
{
  extern int optimize;
  rtx tmp;

  tmp = make_insn_raw (gen_rtx (SET,
				VOIDmode,
				operands [0],
				replace_rtx (copy_rtx (operands [2]),
					     operands [0],
					     operands [1])));

  final_scan_insn (tmp, asm_out_file, optimize, 0, 1);

  return \"\";
}"
  [(set_attr "length" "0")])

(define_peephole
  [(set (match_operand 0 "register_operand" "=r")
	(match_operand 1 "register_operand" "r"))
   (parallel [(set (match_dup 0)
		   (match_operand 2 "" ""))
	      (clobber (match_operand 3 "" ""))
	      (clobber (match_operand 4 "" ""))
	      (clobber (match_operand 5 "" ""))])]
  ""
  "*
{
  extern int optimize;
  rtx tmp;

  tmp = make_insn_raw (gen_rtx (SET,
				VOIDmode,
				operands [0],
				replace_rtx (copy_rtx (operands [2]),
					     operands [0],
					     operands [1])));

  final_scan_insn (tmp, asm_out_file, optimize, 0, 1);

  return \"\";
}"
  [(set_attr "length" "0")])

(define_peephole
  [(set (match_operand 0 "register_operand" "=r")
	(match_operand 1 "register_operand" "r"))
   (parallel [(set (match_dup 0)
		   (match_operand 2 "" ""))
	      (clobber (match_operand 3 "" ""))
	      (clobber (match_operand 4 "" ""))
	      (clobber (match_operand 5 "" ""))
	      (clobber (match_operand 6 "" ""))])]
  ""
  "*
{
  extern int optimize;
  rtx tmp;

  tmp = make_insn_raw (gen_rtx (SET,
				VOIDmode,
				operands [0],
				replace_rtx (copy_rtx (operands [2]),
					     operands [0],
					     operands [1])));

  final_scan_insn (tmp, asm_out_file, optimize, 0, 1);

  return \"\";
}"
  [(set_attr "length" "0")])

(define_peephole
  [(set (match_operand 0 "register_operand" "=r")
	(match_operand 1 "register_operand" "r"))
   (parallel [(set (match_dup 0)
		   (match_operand 2 "" ""))
	      (clobber (match_operand 3 "" ""))
	      (clobber (match_operand 4 "" ""))
	      (clobber (match_operand 5 "" ""))
	      (clobber (match_operand 6 "" ""))
	      (clobber (match_operand 7 "" ""))])]
  ""
  "*
{
  extern int optimize;
  rtx tmp;

  tmp = make_insn_raw (gen_rtx (SET,
				VOIDmode,
				operands [0],
				replace_rtx (copy_rtx (operands [2]),
					     operands [0],
					     operands [1])));

  final_scan_insn (tmp, asm_out_file, optimize, 0, 1);

  return \"\";
}"
  [(set_attr "length" "0")])