Problem 4 - Digital Design

Consider the following design requirements of a sequence circuit using AND, OR, and NOT gate as well as D flip-flop.

Requirements It has a reset signal input and a counter signal input. It outputs a number from zero to eight. When a reset signal is input, the output is reset to zero. When a counter signal is input, the output changes in the following order: 0, 1, 3, 6, 7, 2. After that, the output returns to zero, being in the same state as after a reset signal is input. When both a reset signal and a counter signal are input at the same time, the reset signal is effective.

1.

Show the state transition diagram for this circuit. (Either the Mealy diagram or the Moore diagram is fine.)

2.

Show the truth table of an input variable (a signal variable) of D flip-flop.

3.

Show the logical formula optimized using a Karnaugh diagram or any other tableau method.

4.

Show the whole circuit.

1.

We are about to design a counter whose repeated sequence is:

$$0 = (000)_2$$

$$1 = (001)_2$$

$$3 = (011)_2$$

$$6 = (110)_2$$

$$7 = (111)_2$$

$$2 = (010)_2$$

The state transition diagram considers both the count pulses and the reset signal as external inputs. X is a don't-care condition that expresses the priority of the reset input over the count pulses.

2.

A D flip-flop is also known as a data flip-flop. Indeed, no matter what the state of the flip-flop was, after the occurrence of a count pulse, the flip-flop will be given the value of its D input, as if it was only passing datas from its input to its output.

3.

To find out the logical formula and its eventual optimization, we first build the excitation table of the designed counter. We design the three D flip-flops thanks to the letters $C$,$B$, and $A$, each representing one bit of the state.

$$\begin{tabular}{c c c c c \vert c c c \vert c c c} \multicolumn{5... ...e} & \multicolumn{3}{\vert l}{(Next state/Flip-flop inputs)} \\ \end{tabular}$$

$$\begin{tabular}{c c c c c \vert c c c \vert c c c} $C$ & $B$ & $A... ... 1 & 0 \\ 0 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 \\ \hline \end{tabular}$$

Each of the output can then be expressed as an optimzed Boolean function by means of the following Karnaugh maps. We use the fact that we bever have $100$ and $101$ as states, so that a large part of the Karnaugh maps can be considered as a don't-care condition.

4.

The logic diagram is then derived from the form of the Boolean functions.